FIG. 1 illustrates an exemplary analog-to-digital converter ADC which is based on the successive approximation SAR principle. Typically, such an ADC comprises an analog voltage comparator 12 for comparing an analog input voltage to the output of an internal digital-to-analog converter DAC 11 and for outputting the result of the comparison to a SAR logic unit 10. Although FIG. 1 shows a circuit alternative in which the analog input voltage is applied via a multiplexer 13, switching elements 14 and capacitor 16 to the same input terminal of comparator 12 to which also the output of the DAC 11 is connected (also via switching elements 14 and capacitor 16), it may be assumed that—in a simplified design of the ADC—the analog input voltage and the output signal of the DAC 11 are applied to two different terminals of the comparator 12. For example, the analog input voltage may be applied to the inverting input of the comparator 12 and the output voltage of the DAC 11 may be applied to the non-inverting input of the comparator 12, or vice versa.
In the following, an overview of the SAR algorithm is given with reference to the example circuit depicted in FIG. 1. The SAR logic unit 10 is initialized so that the most significant bit (MSB) is equal to a digital 1. In FIG. 1 for example, bit D7 may be set to 1, while the remaining bits D6 to D0 are set to 0. This digital code D7-D0 is fed to the DAC 11, which then supplies the analog equivalent of this digital code to the comparator 12 for comparison with the analog input voltage. If the output voltage of the DAC 11 exceeds the analog input voltage, the comparator 12 causes the SAR logic unit 10 to reset this bit; otherwise, the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuing this binary search until every bit D7-D0 has been tested. The resulting code D7-D0 is the digital approximation of the analog input voltage and is finally output by the ADC as an 8-bit result at the end of the conversion.
Typically, the digital output signal provided by the ADC converter needs to be calibrated to compensate for variations in the design and/or to map the digital output signal to a desired range. For instance, the analog input signal may represent a temperature measurement and the raw data of the digital output signal needs to be mapped to degree centigrade. For this purpose, a slope correction factor as well as an offset may be determined for calibrating the digital output signal accordingly. In general, both slope correction factor and offset may be determined in a pre-operational phase of the ADC by analyzing at least two non-calibrated conversion results of the ADC. During operation of the ADC, the digital output signal of the DAC 11 is multiplied with the determined slope correction factor in multiplier 18 and the determined offset is added to this signal in adder 19.
However, current ADC calibration and mapping techniques require a separate block to perform the desired operations, i.e. the multiplication in multiplier 18 and the addition in adder 19. Moreover, these operations are performed after the result is provided by the actual ADC converter, i.e. after the result is provided by the DAC 11 in FIG. 1. These additional operations, in particular the multiplication, are costly due to the required space of multiplier 18 and involve an additional time delay. Moreover, the space required for the additional multiplier 18 substantially increases as the number of bits of the digital output signal increases.